Increasing SoC Dependability via Known Good Tile NoC Testing
نویسندگان
چکیده
Advanced CMOS technology possibilities, power, communication and flexibility issues as well as the design gap are directing System-on-Chip (SoC) platforms towards Network-on-Chip (NoC) interconnected identical processing tiles (PT) such as the Montium processor [1]. It is broadly acknowledged that advanced technologies below 45nm come with significant yield and reliability problems, necessitating dependable designs [2]. Our approach for a dependable SoC heavily depends on the regularity within our streaming-data applications SoC. The chip consists of many identical NoC segments and identical PT’s. Boundary condition is that target applications do not require all available fault-free resources, such as routing segments and PTs.
منابع مشابه
System-Level Design of NoC-Based Dependable Embedded Systems
Technology scaling into subnanometer range will have impact on the manufacturing yield and quality. At the same time, complexity and communication requirements of systems-on-chip (SoC) are increasing, thus making a SoC designer goal to design a fault-free system a very difficult task. Network-on-chip (NoC) has been proposed as one of the alternatives to solve some of the on-chip communication p...
متن کاملDesign of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding
Network on Chip (NoC) is an enabling methodology of integrating a very high number of intellectual property (IP) blocks in a single System on Chip (SoC). A major challenge that NoC design is expected to face is the intrinsic unreliability of the interconnect infrastructure under technology limitations. Research must address the combination of new device-level defects or error-prone technologies...
متن کاملFormal Proof of the Dependable Bypassing Routing Algorithm Suitable for Adaptive Networks on Chip QnoC Architecture
Approaches for the design of fault tolerant Network-on-Chip (NoC) for use in System-on-Chip (SoC) reconfigurable technology using Field-Programmable Gate Array (FPGA) technology are challenging, especially in Multiprocessor System-on-Chip (MPSoC) design. To achieve this, the use of rigorous formal approaches, based on incremental design and proof theory, has become an essential step in the vali...
متن کاملShufle-Exchange Mesh Topology for Networks-on-Chip
Network-on-Chip (NoC) is a promising communication paradigm for multiprocessor system-on-chips. This communication paradigm has been inspired from the packet-based communication networks and aims at overcoming the performance and scalability problems of the shared buses in multi-core SoCs (System on Chips)(Benini & Mecheli, 2002). Although the concept of NoCs is inspired from the traditional in...
متن کاملOdelling and Analysis Based on Dynamic Routing
Increasing heterogeneous software and hardware blocks constitute complex ICs known as System on Chip (SoC). These blocks are conceived as intellectual property (IP) cores. Designers are developing SoCs by using IP cores reuse, which include interconnection architecture and interface to peripheral devices.Because of the SoC growing complexity, some researchers tend to concentrate more on the com...
متن کامل